As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
High current information handling system loads, such as for CPU's and memory, typically require multi-phase voltage regulators (VR's). An integrated power stage (IPstage) of each VR phase is an integrated circuit that is usually composed of a MOSFET (metal oxide semiconductor field effect transistor) driver, a high-side MOSFET, and a low-side MOSFET. In addition to an IPstage, a VR phase also usually includes an inductor with all the phase inductors being tied together at their output. One example of a multi-phase VR architecture may be found in U.S. Pat. No. 7,999,520. Generally, each MOSFET supplier for integrated power stages uses a different silicon process for fabrication. Different silicon processes result in a different MOSFET drain to source resistance in on-state or RDS(on) characteristics as a function of gate drive voltage or gate-to-source voltage (VGS).
Servers are a type of information handling system that is requiring ever increasing accuracy for power telemetry data to be used in system level power and thermal management algorithms. For example, CPU power management algorithms poll CPU load current information from a Vcore Voltage Regulator (VR) in order to optimize CPU performance versus power consumption while still maintaining safe operation of the system. Power measurement is required from a system VR with data reported over a serial voltage identification (SVID) bus between the VR controller and the CPU. Accuracy of current sense directly impacts system performance, power saving and reliability. Consequently, tighter current-sense accuracy targets are being presented by CPU manufacturers, e.g., such as +/−10% for 1-5% of maximum load, +/−5% for 5-30% of maximum load, and +/−3% for 30-100% maximum load.
Inductor direct current resistance (DCR) sense has been widely used in the power industry for many years. Considering second source parameter mismatch and additional tolerance from soldering, actual DCR tolerance (TOL) used for current sense may be up to 8% given a 5% TOL inductor. Consequently, current sense tolerance over load range for a conventional high accuracy digital VR controller is not capable of meeting new accuracy standards defined by CPU manufacturers for various loading range segments. Production VR calibration has been proposed to improve current sense accuracy as described in U.S. patent application Ser. No. 13/768,357, filed Feb. 15, 2013.
Discrete power stages (separate dual FET and FET driver packages), including DrMOS, have been traditionally used for main-stream server systems, and inductor DCR current sense is employed. Another possible approach to improving current sense accuracy is to use smart power stage (SPS) technology with RDS(on) current-sensing and calibration, which is an emerging technology. SPS is an industrial trend since it brings simplified circuitry, better current sense accuracy (typical 4-5%), stronger current sensed signal (˜18 times larger than direct current resistance DCR), higher efficiency and higher power density for future high performance VR design.
There are two categories of current sense approaches being used in smart IPstages, i.e., mirror FET sense and RDS(on) sense. However, layout implementation is difficult for currently available smart IPstages. Some of control components have to be placed close to noisy switching node. Moreover, it is still hard to achieve current-sense accuracy targets now being defined by CPU manufacturers. Up to a 50% extra premium fee is required for tighter accuracy IPstages in which monolithic die and mirror FET current sense technique are used. It is also hard to enable the use of multiple types of smart power stages for a given multi-phase VR system due to complex current sense calibration circuitry implementation and interface requirements. As a result, a sole source supply for both VR controller and IPstage are often used for a multi-phase VR system design, which results in higher costs. Additionally, it is almost impossible to use one set of optimal parameters in a digital VR controller of a VR system to accommodate different supplier's IPstages when considering parameter mismatch, different layouts and noisy environment.